Latch circuits, such as MUX latches, are widely used in various electronic products, such as memory devices. For instance, latch circuits may be used at memory outputs to hold data between cycles. This allows the memory cells to be disabled to save power. Moreover, latch circuits may also be used with precharge logic to speed up the access time of memory devices.
A conventional MUX latch is shown in FIG. 1. The conventional MUX latch 100 is used in a memory device. The data output from a core of the memory includes two sets of signals, data (dat0–datn) and their complements (dat_b0–dat_bn). The number of signals is determined by the number of memory banks that the memory is divided into. Typically, one data signal and its complement are output from each memory bank. In the reset state of the memory device, these signals are typically charged to a power supply Vcc. Depending upon the value of the data being read (1 or 0) and the bank being accessed, one of these signals is driven to Vgnd. The MUX latch 100 determines which input has discharged to Vgnd and holds the appropriate logic state even after all inputs have returned to Vcc.
The MUX latch 100 has a four-input pairs (dat0 to dat3 and dat0_b to dat3_b) MUX 110. The MUX latch 100 also has a latch 120 having two inverters 121 and 123, which are embedded inside the MUX 110. The latch 120 stores the previously read data value when the inputs are reset. When one of the input signals to the MUX 110 falls, either node d0 or node d1 is pulled up to Vcc and this value is stored in the latch 120. The MUX latch 100 further includes a five-input NAND gate 130 driven by the signal at node d0 and the signals dat0 through dat3. The NAND gate 130 causes the output signal qout 150 to begin switching before the nodes d0 and d1 reach their final values. This helps to prevent the set time of the latch 120 from being added to the propagation delay through the MUX latch 100.
However, the conventional MUX latch 100 in FIG. 1 suffers from some disadvantages as well. Typically, the five-input NAND gate 130 has a stack of five n-type Metal Oxide Semiconductor (nMOS) devices in its pull down path. This path is hence highly resistive and also has capacitive loading in its four intermediate nodes. If the nMOS devices are sized up to reduce path resistance, then gate capacitance of the nMOS devices increases and hence, node d0 is loaded by the extra gate capacitance. Also, in the worst case, a single p-type Metal Oxide Semiconductor (pMOS) transistor of the NAND gate 130 has to pull up the four intermediate nodes of its pull down path up to Vcc. This parasitic capacitance turns out to be significant and in order to get substantially equal rise and fall delays, the pMOS transistor size in the NAND gate 130 has to be made about 1.1× the size of the nMOS device instead of the expected 0.4×(2/5) factor. This further increases the capacitance of node d0, leading to more delay in the output transition of the MUX latch 100.